Managing annealing pattern effects in 45nm Low Power CMOS technology

ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

Volumn , Issue , 2009, Pages 288-291

  Morin, P ^a   Cacho, F ^a   Beneyton, R ^a   Dumont, B ^a   Bidaud, M ^a   Josse, E ^a   Gallon, C ^a   Ranica, R ^a   Villaret, A ^a   Bianchini, R ^a   Devoivre, T ^a   Serret, E ^a   Binger, R ^a   Barla, K ^a   Haond, M ^a   Colin, A ^a   Bono, H ^b   Chaton, C ^b  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE SENSITIVITY; ELECTRICAL MEASUREMENT; FIELD TEMPERATURE; LOW POWER CMOS; OPTICAL DISPERSION; PATTERN EFFECT; THERMAL SIMULATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 72849113588     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2009.5331536     Document Type: Conference Paper

References (9)

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4. th IEEE International Conference on Advances Thermal Processing of Semiconductors (2002)
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