Simulation of the sub-melt laser anneal process in 45 CMOS technology-Application to the thermal pattern effects

Materials Science and Engineering: B

Volumn 154-155, Issue 1-3, 2008, Pages 31-34

  Colin, A ^a,b   Morin, P ^a   Cacho, F ^a   Bono, H ^c   Beneyton, R ^a   Bidaud, M ^a   Mathiot, D ^b   Fogarassy, E ^b  

^a STMICROELECTRONICS   (France)

^b CNRS   (France)

^c CEA LETI   (France)

Author keywords

CMOS; Junctions; Laser annealing

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; HEAT TRANSFER; LIGHT ABSORPTION; OPTICAL PROPERTIES; SILICON COMPOUNDS; SILICON WAFERS; TEMPERATURE DISTRIBUTION;

ANNEAL PROCESS; CMOS; CMOS TECHNOLOGY; JUNCTION; LASER-ANNEALING; PATTERN EFFECT; SUB-MELT LASER ANNEAL; TEMPERATURE VARIATION; THERMAL PATTERNS; TRENCH ISOLATION;

SILICON OXIDES;

EID: 56949106786     PISSN: 09215107     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mseb.2008.09.009     Document Type: Article

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