Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip

Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009

Volumn , Issue , 2009, Pages 481-490

  Stuart, Matthias Bo ^a   Stensgaard, Mikkel Bystrup ^a   Sparsø, Jens ^a  

^a TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

Author keywords

Configuration; Mapping; Network on chip; Routing; Synthesis; System on chip

Indexed keywords

APPLICATION SPECIFIC; APPLICATION SPECIFIC ROUTING; CIRCUIT SWITCHING; DEADLOCK FREE; DEADLOCK-FREE ROUTING; GENERIC PLATFORMS; GENERIC SYSTEM; NETWORK ON CHIP; NOVEL ALGORITHM; PHYSICAL ARCHITECTURE; POWER CONSUMPTION; POWER EFFICIENT; RE-CONFIGURABLE; SYNTHETIC APPLICATION; SYSTEM ON CHIPS; SYSTEMS ON CHIPS; TOPOLOGY CONFIGURATIONS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; PACKET SWITCHING; PROGRAMMABLE LOGIC CONTROLLERS; TOPOLOGY;

ROUTING ALGORITHMS;

EID: 72149098814     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629435.1629500     Document Type: Conference Paper

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