Improving VLIW processor performance using three-dimensional (3D) DRAM stacking

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2009, Pages 38-45

  Pan, Yangyang ^a   Zhang, Tong ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D STACKING; 3D STACKING TECHNOLOGY; 3D TECHNOLOGY; CLUSTERS SYSTEM; COMPUTING SYSTEM; DIE AREA; HIGH-CAPACITY; L2 CACHE; LOW-LATENCY; MAIN MEMORY; MEMORY ARCHITECTURE; OFF-CHIP; PRIMARY MEMORY; PROCESSING CLUSTERS; SIMULATION RESULT; THREE-DIMENSIONAL (3D); VLIW PROCESSOR; WORK STUDY;

CACHE MEMORY; DIES; DYNAMIC RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE; VERY LONG INSTRUCTION WORD ARCHITECTURE;

THREE DIMENSIONAL;

EID: 71049121053     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2009.11     Document Type: Conference Paper

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