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Volumn 56, Issue 11, 2009, Pages 810-814

A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 v

Author keywords

Complementary metal oxide semiconductor (CMOS) analog circuits; Low supply voltage; Modified latch; Terms Comparator; Ultradeep submicrometer (UDSM) CMOS

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; COMPARATORS (OPTICAL); DELAY CIRCUITS; ELECTRIC POWER UTILIZATION; FLIP FLOP CIRCUITS; LOW POWER ELECTRONICS; METALS; MOS DEVICES; OXIDE SEMICONDUCTORS; THRESHOLD VOLTAGE;

EID: 70549113188     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2009.2030357     Document Type: Article
Times cited : (140)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.