A 0.12μm CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6GHz

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 316-318

  Goll, Bernhard ^a   Zimmermann, Horst ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; DIFFERENTIAL AMPLIFIERS; ELECTRIC LOADS; ELECTRIC POWER UTILIZATION; MOS DEVICES; TRANSISTORS;

BIASED LOAD TRANSISTORS; CLOCK LINE; PMOS TRANSISTORS; RESET SWITCHES;

CMOS INTEGRATED CIRCUITS;

EID: 34548827958     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373421     Document Type: Conference Paper

References (5)

1. S. Park, Y. Palaskas and M. P. Flynn, "A4GS/s 4b Flash ADC in 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 570-571, 2006.
2. Y. Okaniwa et al., "A 40-Gb/s CMOS Clocked Comparator with Bandwidth Modulation Technique," IEEE J. Sotid-State Circuits, pp. 1680-1687, Aug., 2005.
3. K.-L. J. Wong and C.-K. K. Yang, "Offset Compensation in Comparators with Minimum Input-Referred Supply Noise," IEEE J. Solid-State Circuits, pp. 837-840, May, 2004.
4. M. Maymandi-Nejad and M. Sachdev, "1-Bit Quantiser with Rail to Rail Input Range for Sub-1V ΔΣ Modulators," Electronics Letters, pp. 894-895, June 12, 2003.
5. B. Wicht, J.-Y. Larguier and D. Schmitt-Landsiedel, "A 1.5V 1.7ns 4k×32 SRAM with a Fully-Differential Auto-Power-Down Current Sense Amplifier," ISSCC Dig. Tech. Papers, pp. 462-463, 2003.