A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 328-330

  Goll, Bernhard ^a   Zimmermann, Horst ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349292806     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977441     Document Type: Conference Paper

References (6)

1. Y. Okaniwa, H. Tamura, M. Kibune, et al., "A 40-Gb/s CMOS Clocked Comparator With Bandwidth Modulation Technique, " IEEE J. Solid-State Circuits, vol.40, no.8, pp. 1680- 1687, Aug., 2005.
2. B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, "Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier, " IEEE J. Solid-State Circuits, vol.39, pp. 1148-1158, July, 2004.
3. K.-L.J. Wong, C.-K.K. Yang, "Offset Compensation in Comparators With Minimum Input-Referred Supply Noise, " IEEE J. Solid-State Circuits, vol.39, no.5, pp. 837-840, May, 2004.
4. D. Schinkel, E. Mensink, E. Kiumperink, et. al, "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time, " ISSCC Dig. Tech. Papers, pp. 314-315, Feb., 2007.
5. B. Goll and H. Zimmermann, "A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz, " ISSCC Dig. Tech. Papers, pp. 316-317, Feb., 2007.
6. B. Goll and H. Zimmermann, "A Clocked, Regenerative Comparator in 0.12μm CMOS with Tunable Sensitivity, " European Solid-State Circuits Conf., pp. 408-411, Sept., 2007.