A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivity

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 408-411

  Goll, Bernhard ^a   Zimmermann, Horst ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPARATORS (OPTICAL); COMPUTER NETWORKS; ERROR ANALYSIS; TECHNOLOGY;

BIT ERROR RATE (BER); CMOS TECHNOLOGIES; EUROPEAN; SOLID-STATE CIRCUITS CONFERENCE; TAIL CURRENTS;

BIT ERROR RATE;

EID: 44849122717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430329     Document Type: Conference Paper

References (9)

1. H. J. M. Veendrick, "The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate", IEEE J. Solid-State Circuits, Vol. 15, No. 2, pp. 169-176, 1980.
2. K. Uyttenhove, M. S. J. Steyaert, "A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25-μm CMOS", IEEE J. Solid-State Circuits, Vol. 38, No. 7, pp. 1115-1122, July 2003.
3. Ch. Paulus, H.-M. Blüthgen, M. Löw, E. Sicheneder, N. Brüls, A. Courtois, M. Tiebout, R. Thewes, "A 4GS/s Flash ADC in 0.13μm CMOS", IEEE Symp. on VLSI Circuits, pp. 420-423, June 2004.
4. K.-L. J. Wong, C.-K. K. Yang, "Offset Compensation in Comparators With Minimum Input-Reffered Supply Noise", IEEE J. Solid-State Circuits, Vol. 39, No. 5, pp. 837-840, 2004.
5. Y.-C. Hung, B.-D. Liu, "1-V CMOS Comparator for Programmable Analog Rank-Order Extractor", IEEE Trans. Circuits and Systems, Vol. 50, No. 5, pp. 673-677, 2000.
6. B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, "Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier", IEEE J. Solid-State Circuits, Vol. 39, pp. 1148-1158, No. 7, 2004.
7. B. Goll, H. Zimmermann, "A Low-Power 4GHz Comparator in 120nm CMOS Technology with a Technique to Tune Resolution", ESSCIRC 2006, pp. 320-323.
8. B. Goll, H. Zimmermann, "A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz", IEEE ISSCC 2007, pp. 316-317.
9. M. Maymandi-Nejad, M. Sachdev, "1-Bit Quantiser with Rail to Rail Input Range for Sub-IV ΔΣ Modulators", IEE Electron. Lett., vol. 39, pp. 894-895, June 2003.