Low-power 6-bit flash ADC for high-speed data converters architectures

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3930-3933

  Ferragina, Vincenzo ^a   Ghittori, Nicola ^a   Maloberti, Franco ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CIRCUIT SIMULATION; FLASH MEMORY; INTERPOLATION; NETWORK ARCHITECTURE;

DATA CONVERTERS ARCHITECTURES; FLASH ADC; V/I CONVERTERS;

ANALOG TO DIGITAL CONVERSION;

EID: 34250717866     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. R.J. Van de Plassche, "Integrated Analog-to-digital and Digital-to-analog Converters," Kluwer Academics Publisher, 1994.
2. R. Roovers and M. Steyaert, "Design of CMOS A/D converters with, folding and/or interpolating technique," Advanced A-D and D-A Conversion Techniques and their Applications, pp. 76-81, July 1994.
3. H. van der Ploeg and R. Rammers, "A 3.3-V, 1.0-b, 25-MSamples/s Two-Step ADC in 0.35-μm CMOS", IEEE. Journal of Solid State Circuits, vol. 34, no. 12, pp. 1803-1811, December 1999.