Concept for body coupling in SOI MOS transistors to improve multi-finger triggering

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2006, Pages 172-178

  Keppens, Bart ^a   Wybo, Geert ^a   Vermont, Gerd ^a   Van Camp, Benjamin ^a  

^a Sarnoff Europe   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR SNAPBACK; ESD PERFORMANCE; FAILURE CURRENTS; FULLY SILICIDED DEVICES; GATE LENGTH; MOS TRANSISTORS; NONUNIFORM; SILICIDE-BLOCKED; SOI TECHNOLOGY;

ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; SEMICONDUCTING SILICON; SILICIDES; SILICON ON INSULATOR TECHNOLOGY; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

MOS DEVICES;

EID: 70450210552     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EOSESD.2006.5256784     Document Type: Conference Paper

References (12)

1. B. Keppens et al., "Active-Area-Segmentation (AAS) Technique for Compact, ESD Robust, Fully Silicided NMOS design", EOS/ESD 2003.
2. Y.-C. Tseng et al., "Local Floating Body Effect in Body-grounded SO1 nMOSFETs", SOI conference 1997
3. M. G. Khazhinsky et al., "ESD protection for advanced CMOS SOI Technologies", EOS/ESD 2005.
4. A. Deckelmann et al., "Optimization of LGate for ggNMOS ESD protection devices fabricated on Bulk- and SOI-Substrates, using Process and Device Simulation", SISPAD 2003.
5. M. Mergens et al., "Multi-Finger Turn-on Circuits and Design Techniques for enhanced ESD performance and width-scaling", EOS/ESD 2001
6. G. Boselli et al., "Analysis of ESD Protection Components in 65nm CMOS Technology: Scaling Perspective and Impact on ESD Design Window", EOS/ESD 2005
7. M. Stockinger et al., "Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies," EOS/ESD 2003
8. O. Marichal et al., "SCR based ESD protection in nanometer SOI technologies", EOS/ESD 2005
9. Y. Oomura, "A lateral, unidirectional, bipolar-type insulated-gate transistor - A novel semiconductor device", Appl. Phys. Lett 40(6), March 1982
10. C. Russ, et al. "GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes", EOS/ESD 2001.
11. M. Mergens, et al., "Diode-Triggered SCR (DTSCR) for RFESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxide", IEDM 2003
12. B. Van Camp et al., "Current detection trigger scheme for SCR based ESD protection of Output drivers in CMOS technologies avoiding competitive triggering," EOS/ESD 2005