Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 1-11

  Mergens, Markus P J ^a   Verhaege, Koen G ^b   Russ, Christian C ^a   Armer, John ^a   Jozwiak, Phillip C ^a   Kolluri, Girija ^a   Avery, Leslie R ^a  

^a SARNOFF CORPORATION   (United States)

^b Sarnoff Europe   (Belgium)

Author keywords

Circuits; Electrostatic discharge

Indexed keywords

DESIGN; ELECTROSTATIC DISCHARGE; INTEGRATED CIRCUIT MANUFACTURE; NETWORKS (CIRCUITS); SEMICONDUCTOR JUNCTIONS; SILICIDES;

BALLAST CIRCUIT; DESIGN TECHNIQUE; ESD PERFORMANCE; ESD PROTECTION; FULLY SILICIDED; ON-RESISTANCE; SELF PROTECTING; SILICIDE-BLOCKED;

ELECTROSTATIC DEVICES;

EID: 84948994333     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. K. Verhaege and C. Russ. Wafer Cost Reduction through Design of High Performance Fully Silicided ESD Devices. EOS/ESD Symposium 2000, pp. 18-28
2. D. Krakauer, et al. ESD Protection in a 3.3V Sub-Micron Silicided CMOS Technology. EOS/ESD Symposium 1992, pp. 250-257
3. A. Amerasekera, et al. ESD Failure Modes: Characteristics, Mechanisms and Process Influences. IEEE TED-39, 1992, p.2
4. G. Notermans, et al. The Effect of Silicide on ESD Performance. IRPS 1999, pp. 154-158
5. HB. Park, et al. A Novel NMOS Transistor for High Performance ESD Protection Devices in a 0.18um CMOS Technology Utilizing Salicide Process. EOS/ESD Symposium 2000, pp. 407-412
6. T. Polgreen, et al. Improving the ESD Failure Threshold of Silicided NMOS Output Transistors by Ensuring Uniform Current Flow, EOS/ESD Symposium 1989, pp. 167-174
7. G. Krieger. Non-Uniform ESD Current Distribution due to Improper Metal Routing, EOS/ESD Symposium 1991, pp. 104-109
8. C. Duvvury, et al. Achieving Uniform nMOS Device Power distribution for Sub-Micron ESD Reliability, IEDM 1992, pp.131-134
9. C. Duvvury, et al. Substrate Pump NMOS for ESD Protection Application. EOS/ESD Symposium 2000, pp. 1828
10. C. Duvvury. Presentation of publication [9] at EOS/ESD Symposium in Anaheim, CA, USA, 2000
11. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, Wiley and Sons, 1995, ISBN 0471 95481 O
12. Russ Mergens, Verhaege Armer, Jozwiak Kolluri Avery. GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Technologies. To be published in proceedings of EOS/ESD Symposium 2001, Portland, USA