SCR based ESD protection in nanometer SOI technologies

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2005, Pages

  Marichal, Olivier ^a   Wybo, Geert ^a   Van Camp, Benjamin ^a   Vanysacker, Pieter ^a   Keppens, Bart ^a  

^a Sarnoff Europe   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ESD PROTECTION; EXPERIMENTAL DATA; SOI TECHNOLOGY;

ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE;

MOS DEVICES;

EID: 70449726741     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. M. Mergens, et al., "Diode-Triggered SCR (DTSCR) for RFESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxide", IEDM 2003 proceedings.
2. P. Raha, et al. "Prediction of ESD Protection Levels and Novel Protection Devices in Thin Film SOI Technology", EOS/ESD 1997 proceedings.
3. M. Chan, et al., "Comparison of ESD Protection Capability of SOI and BULK CMOS Output Buffers", IRPS 1994 proceedings.
4. S. Ramaswamy, et al. "EOS/ESD protection Circuit Design for Deep Submicron SOI Technology", EOS/ESD 1995 proceedings.
5. C. Russ, et al. "GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes", EOS/ESD 2001 proceedings.
6. M.Mergens, et al., "High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC Operation", EOS/ESD 2002 proceedings.
7. B. Van Camp, et al. "Current detection trigger scheme for SCR based ESD protection for output drivers in CMOS technologies avoiding competitive triggering", EOS/ESD 2005 proceedings.