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International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn 2003-January, Issue , 2003, Pages 251-254

Optimization of LGate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation

(2) Deckelmann, A I a Wachutka, G a

a TECHNICAL UNIVERSITY OF MUNICH (Germany)

Author keywords

Calibration; Doping profiles; Electrical resistance measurement; Electrostatic discharge; Electrothermal effects; Fabrication; Physics; Protection; Semiconductor process modeling; Voltage

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; FABRICATION; PHYSICS; SEMICONDUCTOR DOPING; SUBSTRATES;

DOPING PROFILES; ELECTRICAL RESISTANCE MEASUREMENT; ELECTRO-THERMAL EFFECTS; PROTECTION; SEMICONDUCTOR PROCESS MODELING;

SEMICONDUCTOR DEVICES;

EID: 84904171545 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/SISPAD.2003.1233684 Document Type: Conference Paper

Times cited : (5)

References (7)

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2
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- Electrostatic discharge protection in silicon-on-insulator technology
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3
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- ESD protection in thin film silicon on insulator technologies
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- Smith, J.C.¹

4
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- The ESD protection capability of SOI snapback nMOSFETs: Mechanisms and failure modes
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5
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- Characterization and Optimization of a Bipolar ESD- Device by Measurements and Simulations
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6
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7
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- Roulston, D.J.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.