Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2005, Pages

  Boselli, Gianluca ^a   Rodriguez, John ^a   Duvvury, Charvaka ^a   Smith, Jeremy ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; CMOS TECHNOLOGY; ESD PROTECTION; LOW POWER APPLICATION; LOW-VOLTAGE TRANSISTORS; SCALING ANALYSIS; TECHNOLOGY SCALING;

CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DISCHARGE; WINDOWS;

ELECTROSTATIC DEVICES;

EID: 70449715382     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

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