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Volumn , Issue , 2005, Pages

Current detection trigger scheme for SCR based ESD protection of output drivers in CMOS technologies avoiding competitive triggering

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; CURRENT DETECTION; CURRENT FLOWING; ESD PROTECTION; NOVEL SOLUTIONS; OUTPUT DRIVERS; PROTECTION SCHEMES; TRIGGER SCHEMES;

EID: 70449701703     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (17)
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  • 2
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    • HB. Park et al., A Novel NMOS Transistor for High Performance ESD Protection Devices in a 0.18um CMOS Technology, Utilizing Salicide Process, EOS/ESD 2000.
    • HB. Park et al., "A Novel NMOS Transistor for High Performance ESD Protection Devices in a 0.18um CMOS Technology, Utilizing Salicide Process", EOS/ESD 2000.
  • 3
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    • Circuit to improve electrostatic discharge protection
    • US patent 5 019 888
    • D.B. Scott et al., "Circuit to improve electrostatic discharge protection", US patent 5 019 888, 1991
    • (1991)
    • Scott, D.B.1
  • 7
    • 84948994333 scopus 로고    scopus 로고
    • Multi-Finger Turn-on Circuits and Design Techniques for enhanced ESD performance and width-scaling, Proc
    • M. Mergens et al., "Multi-Finger Turn-on Circuits and Design Techniques for enhanced ESD performance and width-scaling", Proc. EOS/ESD 2001, pp. 1-11.
    • (2001) EOS/ESD , pp. 1-11
    • Mergens, M.1
  • 8
    • 0000790344 scopus 로고
    • Improving the ESD Failure Threshold of Silicided NMOS Output Transistors by Ensuring Uniform Current Flow
    • T. Polgreen, et al., Improving the ESD Failure Threshold of Silicided NMOS Output Transistors by Ensuring Uniform Current Flow, EOS/ESD 1989, pp. 167-174.
    • (1989) EOS/ESD , pp. 167-174
    • Polgreen, T.1
  • 9
    • 0031352418 scopus 로고    scopus 로고
    • Design Methodology for Optimizing Gate Drive ESD Protection Circuits in Submicron CMOS Processes
    • Proc. ESD/EOS
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    • (1997) , pp. 230-239
    • Chen, J.Z.1    Amerasekera, A.2    Duvvury, C.3
  • 10
    • 0033279655 scopus 로고    scopus 로고
    • An Anti-Snapback Circuit Technique for Inhibiting Parasitic Bipolar Conduction
    • J.C. Smith, An Anti-Snapback Circuit Technique for Inhibiting Parasitic Bipolar Conduction, EOS/ESD 1999, pp. 62-69
    • (1999) EOS/ESD , pp. 62-69
    • Smith, J.C.1
  • 13
    • 77950846973 scopus 로고    scopus 로고
    • Voltages before and after HBM stress and their effect on dynamically triggered power supply clamps
    • R. Ashton et al. 'Voltages before and after HBM stress and their effect on dynamically triggered power supply clamps', EOS/ESD symposium 2004, p. 153-159
    • (2004) EOS/ESD symposium , pp. 153-159
    • Ashton, R.1
  • 14
    • 77950845126 scopus 로고    scopus 로고
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    • C. Duvvury et al. 'Gate Oxide failures due to anomalous stress from HBM ESD testers', EOS/ESD symposium proceedings 2004, p 132 - 140
    • (2004) EOS/ESD symposium proceedings , pp. 132-140
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  • 15
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    • Standard ESD testing of Integrated Circuits
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    • van Roozendaal, L.1
  • 16
    • 0027844313 scopus 로고    scopus 로고
    • K. Verhaege et al., 'Analysis of HBM ESD Testers And Specifications Using A 4th Order Lumped Element Model', EOS/ESD symposium proceedings 1993, p. 129-138
    • K. Verhaege et al., 'Analysis of HBM ESD Testers And Specifications Using A 4th Order Lumped Element Model', EOS/ESD symposium proceedings 1993, p. 129-138
  • 17
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    • ESD Protection Elements During HBM Stress Tests - Further Numerical And Experimental Results
    • C. Russ et al., 'ESD Protection Elements During HBM Stress Tests - Further Numerical And Experimental Results', EOS/ESD symposium proceedings 1994, p 96-10
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.