Chip to chip bonding using micro-Cu bumps with Sn capping layers

2009 European Microelectronics and Packaging Conference, EMPC 2009

Volumn , Issue , 2009, Pages

  Lee, Jin Soo ^b   Byun, Kwang Yoo ^a   Chung, Qwan Ho ^a   Suh, Min Suk ^a   Kim, Seong Cheol ^a   Kim, Young Ho ^b  

^a Hynix Semiconductor Inc   (South Korea)

^b Hanyang University   (South Korea)

Author keywords

Lead free; Micro bump; Shear test; Sn Ag; TSV

Indexed keywords

3D-CHIP STACKING TECHNOLOGY; BONDING CONDITIONS; CAPPING LAYER; CHIP BONDING; CU BUMPS; LEAD-FREE; MICRO VOIDS; MICRO-BUMPS; PHASE-ONLY; RICH PHASE; SN-AG SOLDER; THERMO-COMPRESSION;

BONDING; CHIP SCALE PACKAGES; FLIP CHIP DEVICES; MICROELECTRONICS; MICROSTRUCTURE; PHASE INTERFACES; SHEAR STRENGTH; SILVER;

TIN;

EID: 70449746815     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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