Evaluating design tradeoffs in on-chip power management for CMPs

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 44-49

  Sharkey, Joseph ^a,b   Buyuktosunoglu, Alper ^a   Bose, Pradip ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Assured Information Security Inc   (United States)

Author keywords

Chip multi processor; Dynamic voltage scaling; Fetch throttling; Power aware

Indexed keywords

CHIP MULTI PROCESSORS; DYNAMIC VOLTAGE SCALING; FETCH THROTTLING;

COMPUTER HARDWARE; COMPUTER SIMULATION; ENERGY DISSIPATION; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

MULTIPROCESSING SYSTEMS;

EID: 36949022431     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283791     Document Type: Conference Paper

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