DDCache: Decoupled and delegable cache data and metadata

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 227-236

  Hossain, Hemayet ^a   Dwarkadas, Sandhya ^a   Huang, Michael C ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

Cache coherence; Chip multiprocessors; DDCache; Decoupled cache; Delegable cache

Indexed keywords

BANDWIDTH RESOURCE; BASE SYSTEMS; CACHE ACCESS; CACHE CAPACITY; CACHE COHERENCE; CACHE COHERENCE PROTOCOLS; CACHE DATA; CHIP MULTIPROCESSOR; COMMUNICATION OVERHEADS; DATA AND METADATA; DATA REPLICATION; DATA SPACE; FULL-SYSTEM SIMULATION; FUTURE DESIGNS; GEOMETRIC MEAN; INTERACTING PROCESS; MANY-CORE; MICROBENCHMARKS; NONUNIFORM; OFF-CHIP; ON CHIP COMMUNICATION; ON CHIP MEMORY; ON CHIPS; ON-CHIP CACHE; SPACE UTILIZATION;

MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARALLEL ARCHITECTURES;

METADATA;

EID: 70449669476     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.24     Document Type: Conference Paper

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