ITCA: Inter-task conflict-aware CPU accounting for CMPs

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 203-213

  Luque, Carlos ^a   Moreto, Miquel ^b   Cazorla, Francisco J ^a   Gioiosa, Roberto ^c   Buyuktosunoglu, Alper ^c   Valero, Mateo ^b  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

ATD; Cache partitioning algorithms; Chip multiprocessor; Cycle accounting; Fairness

Indexed keywords

APPLICATION SCHEDULING; AVERAGE ERRORS; CACHE PARTITIONING; CHARGING MECHANISM; CHIP-MULTIPROCESSOR; CORE PROCESSORS; CPU UTILIZATION; DATA CENTERS; INSTRUCTION LEVEL PARALLELISM; OTHER APPLICATIONS;

ELECTRIC CHARGE; PARALLEL ARCHITECTURES;

MULTIPROCESSING SYSTEMS;

EID: 70449626078     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.33     Document Type: Conference Paper

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