CPU accounting in CMP processors

IEEE Computer Architecture Letters

Volumn 8, Issue 1, 2009, Pages 17-20

  Luque, Carlos ^a   Moreto, Miquel ^a   Cazorla, Francisco J ^b   Gioiosa, Roberto ^c   Buyuktosunoglu, Alper ^c   Valero, Mateo ^a,b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE ERRORS; CHARGING MECHANISM; CHIP-MULTIPROCESSOR; CORE PROCESSORS; CPU UTILIZATION; DATA CENTERS; IN-CHIP; PROCESS SCHEDULING;

ELECTRIC CHARGE; MULTIPROCESSING SYSTEMS;

NANOTECHNOLOGY;

EID: 67650577174     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2009.3     Document Type: Article

References (11)

1. Acosta et al. The MPsim simulation tool. Technical Report UPC-DAC-RR-2009-7, 2009.
2. Cazorla et al. Architectural support for real-time task scheduling in SMT systems. In CASES, 2005.
3. Cazorla et al. Predictable performance in SMT processors: Synergy between the OS and SMTs. IEEE Trans. Computers, 2006.
4. Eyerman et al. Per-thread cycle accounting in SMT processors. In ASPLOS, 2009.
5. Fedorova et al. Improving performance isolation on chip multiprocessors via an operating system scheduler. In PACT, 2007.
6. Iyer et al. QoS policies and architecture for cache/memory in CMP platforms. In SIGMETRICS, 2007.
7. Jaleel et al. Adaptive insertion policies for managing shared caches. In PACT , 2008.
8. Kim et al. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT, 2004.
9. Nesbit et al. Virtual private caches. In ISCA, 2007.
10. Qureshi et al. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO, 2006.
11. Sherwood et al. Basic block distribution analysis to find periodic behavior and simulation points in applications. In PACT, 2001.