Operating system exploitation of the POWER5 system

IBM Journal of Research and Development

Volumn 49, Issue 4-5, 2005, Pages 533-539

  Mackerras, Paul ^a   Mathews, Thomas S ^b   Swanberg, Randal C ^b  

^a IBM Australia   (Australia)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; OPTIMIZATION; SYNCHRONIZATION;

INSTRUCTION CACHE; SIMULTANEOUS MULTITHREADING; TRANSLATION LOOKASIDE BUFFER; VIRTUAL PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 25844520764     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.494.0533     Document Type: Article

References (4)

1. R. Kalla, B. Sinharoy, and J. M. Tendler, "IBM POWER5 Chip: A Dual-Core Multithreaded Processor," IEEE Micro 24, 40-47 (March-April 2004).
2. J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, "POWER4 System Microarchitecture," IBM J. Res. & Dev. 46, No. 1, 5-26 (January 2002).
3. The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, C. May, E. Silha, R. Simpson, and H. Warren, Eds., Morgan Kaufmann Publishers, Inc., San Francisco, 1994.
4. J. M. Borkenhagen, R. J. Eickemeyer, R. N. Kalla, and S. R. Kunkel, "A Multithreaded PowerPC Processor for Commercial Servers," IBM J. Res. & Dev. 44, No. 6, 885-898 (November 2000).