32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 84-85

  Takemura, R ^a   Kawahara, T ^a   Miura, K ^a,b   Yamamoto, H ^a,b   Hayakawa, J ^a   Matsuzaki, N ^a   Ono, K ^a   Yamanouchi, M ^a   Ito, K ^a   Takahashi, H ^a   Ikeda, S ^b   Hasegawa, H ^a,b   Matsuoka, H ^a   Ohno, H ^b  

^a HITACHI LTD   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS TIME; BI-DIRECTIONAL; CELL SIZE; LARGE-SCALE ARRAYS; LINE STRUCTURES; MAGNETORESISTIVE DEVICES; MEMORY CELL; READ OPERATION; SPIN TRANSFER TORQUE; SUPPLY VOLTAGES; WRITING CURRENTS;

VLSI CIRCUITS;

EID: 70449393678     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. T. Kawahara, et al., ISSCC Tech. Dig., 2007 pp.480-481.
2. K. Miura, et al., VLSI Tech. Dig., 2007, pp. 234-235.