Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30 nm low-power high-speed solid-state drives (SSD)

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 4, 2009, Pages 1227-1234

  Takeuchi, Ken ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

Flash memory; NAND controller; NAND flash memory; Solid state drive; SSD

Indexed keywords

CONTROLLERS; DATA STORAGE EQUIPMENT; DRIVES; INTEGRATED CIRCUITS; NAND CIRCUITS; PERSONAL COMPUTERS; SPEED;

BIT LINES; CELL SIZES; CIRCUIT NOISE; CIRCUIT TECHNOLOGIES; CO DESIGNS; COST PENALTIES; CURRENT CONSUMPTION; CURRENT PEAKS; DIE SIZES; ENTERPRISE SERVERS; HIGH-SPEED; LINE STRUCTURES; LOAD CAPACITANCES; LOW-POWER; MASS STORAGES; MEMORY CAPACITIES; NAND CONTROLLER; NAND FLASH MEMORY; NAND FLASHES; PRE CHARGES; PROGRAM SCHEMES; SSD; WRITE OPERATIONS;

FLASH MEMORY;

EID: 63449104097     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2014027     Document Type: Conference Paper

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