Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

Cryogenics

Volumn 49, Issue 11, 2009, Pages 599-604

  de Souza, Michelly ^a,b   Flandre, Denis ^c   Pavanello, Marcelo Antonio ^a,b  

^a CENTRO UNIVERSITÁRIO DA FEI   (Brazil)

^b UNIVERSITY OF SÃO PAULO   (Brazil)

^c UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

A. Semiconductors; D. Cryoelectronics

Indexed keywords

A. SEMICONDUCTORS; CHANNEL LENGTH; CONSTANT GAIN; CRYOGENIC TEMPERATURES; D. CRYOELECTRONICS; EFFECTIVE CHANNEL LENGTH; FULLY DEPLETED; INPUT VOLTAGES; INVERSION LEVELS; LOW TEMPERATURES; MAXIMUM VALUES; MOSFETS; NMOS TRANSISTORS; SOI N-MOSFETS; TWO-DIMENSIONAL NUMERICAL SIMULATION; VOLTAGE GAIN; WORK STUDY;

BOLOMETERS; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; LOW TEMPERATURE ENGINEERING; MOSFET DEVICES; SEMICONDUCTOR QUANTUM DOTS; STANDARDS; SUPERCONDUCTIVITY;

TRANSISTORS;

EID: 70350609881     PISSN: 00112275     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.cryogenics.2008.12.010     Document Type: Article

References (25)

1. Laker K.R., and Sansen W.M.C. Design of analog integrated circuits and systems. 1st ed. (1994), McGraw-Hill
2. Fossum E. CMOS image sensors: electronic camera on a chip. IEDM Tech Dig (1995) 17-25
3. Fan X., and Chan P.K. Analysis and design of low-distortion CMOS source followers. IEEE Trans Circ Syst 52 8 (2005) 1489-1501
4. Zin MAM, Kobayashi H, Kobayashi K, Ichimure JI, San H, Onaya Y, et al. A high-speed CMOS track/hold circuit. In: Proceedings of the 6th IEEE international conference on electronics, circuits and systems; 1999. p. 1709-12.
5. Park S., Uh H., and Choi S. A high-sensitivity CCD image sensor using source follower circuit with actively controlled gain characteristics. Sensors Actuat 101 1 (2002) 10-13
6. Razavi B. Design of analog CMOS integrated circuits (2002), McGraw-Hill
7. Afzalian A., and Flandre D. Modeling of the bulk versus SOI CMOS performances for the optimal design of aps circuits in low-power low-voltage applications. IEEE Trans Electron Dev 50 1 (2003) 106-110
8. Colinge J.P. Fully-depleted SOI CMOS for analog applications. IEEE Trans Electron Dev 45 5 (1998) 1010-1016
9. Flandre D., Eggermont J.P., De Ceuster D., and Jespers P. Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs. Electron Lett 30 23 (1994) 1933-1934
10. Choi J.I., and Fossum J.G. Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFETs. IEEE Trans Electron Dev 38 6 (1991) 1384-1391
11. Pavanello M.A., Martino J.A., Dessard V., and Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electron 44 7 (2000) 1219-1222
12. Pavanello M.A., Martino J.A., and Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electron 44 6 (2000) 917-922
13. Pavanello M.A., Martino J.A., and Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electron 46 8 (2002) 1215-1225
14. Tarui Y., Hayashi Y., and Sekigawa T. Diffusion self-aligned MOST: a new approach for high speed devices. J Jpn Soc Appl Phys 39 (1997) 105-110
15. Buti T.N., Ogura S., Rovedo N., and Tobimatsu K. A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance. IEEE Trans Electron Dev 38 8 (1991) 1757-1764
16. Shen C.C., Murgia J., Goldsman N., Peckerar M., Melganilis J., and Antoniadis D. Use of focused-ion-beam and modeling to optimize submicron MOSFET characteristics. IEEE Trans Electron Dev 45 2 (1998) 453-459
17. Hiroki A., Odanaka S., and Hori A. A high performance 01 μm MOSFET with asymmetric channel profile. IEDM Tech Dig (1995) 439-442
18. Cheng B, Ramgopal Rao V, Woo JCS. Sub-0.18 μm SOI MOSFET using lateral asymmetric channel profile and Ge pre-amorphization salicide technology. In: Proceedings of IEEE international SOI conference; 1998. p. 113-4.
19. Cerdeira A., Aleman M.A., Pavanello M.A., Martino J.A., Vancaillie L., and Flandre D. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Trans Electron Dev 52 4 (2005) 967-972
20. Pavanello M.A., Agopian P.G.D., Martino J.A., and Flandre D. Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. Microelectron J 37 2 (2006) 137-144
21. de Souza M., Flandre D., and Pavanello M.A. Advantages of graded-channel SOI NMOSFETS for application as source-follower analog buffer. Solid-State Electron 52 12 (2008) 1933-1938
22. Shoucair F.S. Analytical and experimental methods for zero-temperature-coefficient biasing of MOS transistors. Electron Lett 25 17 (1989) 1196-1198
23. Veeraraghavan S., and Fossum J.G.A. Short-channel effects in SOI MOSFETs. IEEE Trans Electron Dev 36 3 (1989) 522-528
24. ATLAS. User's Manual, SILVACO; 2007.
25. de Souza M, Pavanello MA, Flandre D. Submicrometer graded-channel SOI MOSFET modeling for low temperature analog circuit design. In: Proceedings of the 7th international workshop on low temperature electronics (WOLTE 7); 2006. p. 57-64.