A feedback-based approach to DVFS in data-flow applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 11, 2009, Pages 1691-1704

  Alimonda, Andrea ^a   Carta, Salvatore ^a   Acquaviva, Andrea ^b   Pisano, Alessandro ^a   Benini, Luca ^c  

^a UNIVERSITY OF CAGLIARI   (Italy)

^b POLITECNICO DI TORINO   (Italy)

^c UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Data flow; Dynamic voltage scaling (DVS); Energy management; Feedback control; Streaming

Indexed keywords

CONTROL APPROACH; CONTROL-THEORETIC APPROACH; CYCLE ACCURATE; DATA ENCRYPTION STANDARD; DATA FLOW; DATAFLOW MODEL; DYNAMIC FREQUENCY; DYNAMIC VOLTAGE SCALING (DVS); DYNAMIC VOLTAGE/FREQUENCY SCALING; ENERGY AWARE; MULTI CORE; MULTIPROCESSOR SIMULATION; MULTIPROCESSOR SYSTEMS ON CHIPS; NON LINEAR CONTROL; PROCESSING SPEED; RUNTIMES; SOFTWARE-BASED; STREAMING; STREAMING APPLICATIONS; WORKLOAD VARIATION;

CRYPTOGRAPHY; ENERGY MANAGEMENT; FAULT TOLERANCE; FEEDBACK CONTROL; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; SIMULATORS; VOLTAGE STABILIZING CIRCUITS;

FEEDBACK;

EID: 70350594151     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2030439     Document Type: Article

References (37)

1. A. Alimonda, A. Acquaviva, S. Carta, and A. Pisano, "A control theoretic approach to run-time energy optimization of pipelined elaboration in MPSoCs," in Proc. DATE, 2006, pp. 876-877.
2. A. Alimonda, A. Acquaviva, S. Carta, and A. Pisano, "Non-linear feedback control for energy efficient on-chip streaming computation," in Proc. Symp. IES, 2006, pp. 1-8.
3. K. Asanovic, R. Bodik, B. C. Catanzaro, J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: A view from Berkeley," Univ. California, Berkeley, Berkeley, CA, Tech. Rep. UCB/EECS-2006-2183, Dec. 18, 2006.
4. S. Carta, A. Alimonda, A. Acquaviva, A. Pisano, and L. Benini, "A control theoretic approach to energy-efficient pipelined computation in MPSoCs," ACM Trans. Embedded Comput. Syst.(TECS), vol.6, no.4, p. 27, Sep. 2007.
5. A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. M. Al-Hashimi, "Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems," in Proc. ICCAD, 2004, pp. 362-369.
6. A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. M. Al-Hashimi, "Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems," in Proc. DATE, 2004, pp. 518-523.
7. ARM Intelligent Energy Manager, Dynamic Power Control for Portable Devices, 2005. [Online]. Available: http://infocenter.arm.com/ help/topic/com.arm.doc.dai0172b/
8. ARM Ltd., ARM11 MPCore. [Online]. Available: http://www.arm.com/ products/CPUs/ARM11MPCoreMultiprocessor.html
9. Cradle Technologies, Cradle's CT3000 Family. [Online]. Available: http://www.cradle.com/multi-core-dsp.html
10. "Federal information processing standards publication 46-2," Announcing the Standard for DATA ENCRYPTION STANDARD (DES), 1993. [Online]. Available: http://www.itl.nist.gov/fipspubs/fip46-2.htm
11. T. Durnan and C. Pollabauer, "DDVS: Distributed dynamic voltage scaling," in Proc. SOSP, 2005, pp. 1-8.
12. K. Flautner and T.N. Mudge, "Vertigo: Automatic performance-setting for Linux," in Proc. OSDI, 2002, pp. 105-116.
13. Freescale, i.MX31 Multimedia Applications Processors, Austin, TX, 2003. [Online]. Available: http://www.freescale.com/imx31
14. S. V. Gheorghita, T. Basten, and H. Corporaal, "Application scenarios in streaming-oriented embedded system design," in Proc. Int. SoCC, 2006, pp. 175-178.
15. GStreamer: Open Source Multimedia Framework. [Online]. Available: http://gstreamer.freedesktop.org/
16. C. Im, H. Kim, and S. Ha, "Dynamic voltage scaling technique for lowpower multimedia applications using buffers," in Proc. ISLPED, 2001, pp. 34-39.
17. Intel, Intel Multi-Core Processors. [Online]. Available: http://www.intel. com/research/platform/ terascale/ts-microprocessors.htm
18. D. Lackey, P. Zuchowski, T. R. Bedhar, D. W. Stout, S. Gould, and J. Cohn, "Managing power and performance for systems-on-chip designs using voltage islands," in Proc. ICCAD, 2002, pp. 195-202.
19. Z. Lu, J. Lach, and M. Stan, "Reducing multimedia decode power using feedback control," in Proc. ICCD, 2003, pp. 489-496.
20. Y. Lu, L. Benini, and G. De Micheli, "Dynamic frequency scaling with buffer insertion for mixed workloads," IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol.21, no.11, pp. 1284-1305, Nov. 2002.
21. Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron, "Control theoretic dynamic frequency and voltage scaling for multimedia workloads," in Proc. Int. Conf. CASES, 2002, pp. 156-163.
22. Khronos Group-Media Authoring and Acceleration, OpenMAX-The Standard for Media Library Portability. [Online]. Available: http://www. khronos.org/openmax/
23. P. Juang, Q.Wu, L.-S. Peh, M. Martonosi, and D.W. Clark, "Coordinated, distributed, formal energy management of chip multiprocessors," in Proc. ISLPED, 2005, pp. 127-130.
24. Z. Ma and F. Catthoor, "Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platforms," in Proc. DATE, 2006, pp. 1073-1078.
25. R. Teodorescu and J. Torrellas, "Variation-aware application scheduling and power management for chip multiprocessors," SIGARCH Comput. Archit. News, vol.36, no.3, pp. 363-374, 2008.
26. MPARM multiprocessor simulation environment. [Online]. Available: http://www-micrel.deis.unibo.it/sitonew/research/mparm.html
27. N. Pazos, A. Maxiaguine, P. Ienne, and Y. Leblebici, "Parallel modelling paradigm in multimedia applications: Mapping and scheduling onto a multi-processor system-on-chip platform," in Proc. Int. GSP Conf., 2004.
28. D. Pham, S. Asano, M. Bolliger, M. N. Day, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Riley, D. Shippy, D. Stasiak, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, and K. Yazawa, "The design and implementation of a first-generation CELL processor," in Proc. IEEE/ACM ISSCC, 2005, pp. 184-186.
29. M. Ruggiero, A. Acquaviva, D. Bertozzi, and L. Benini, "Applicationspecific power-aware workload allocation for voltage scalable MPSoC platforms," in Proc. ICCD, 2005, pp. 87-93.
30. M. Ruggiero, G. Pari, A. Guerri, D. Bertozzi, M. Milano, L. Benini, and A. Andrei, "A cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MPSoCs," in Proc. Int. SoCC, 2006, pp. 1-4.
31. T. Stefanov, C. Zissulescu, A. Turjan, B. Kienhuis, and E. Deprettere, "System design using Kahn process networks: The Compaan/Laura approach," in Proc. DATE, Mar. 2004, pp. 1530-1591.
32. W. Thies, M. I. Gordon, M. Karczmarek, J. Lin, D. Maze, R. M. Rabbah, and S. Amarasinghe, "Language and compilers design for streaming applications," in Proc. IEEE IPDPS, 2004, p. 201.
33. M. Wesley, J. Johnston, J. Paul Hanna, and R. Miller, "Advances in dataflow programming languages," ACM Comput. Surv., vol.36, no.1, pp. 1-34, Mar. 2004.
34. Q. Wu, P. Juang, M. Martonosi, and W. Clark, "Formal online methods for voltage/frequency control in multiple clock domain microprocessors," in Proc. Int. Conf. ASPLOS, 2004, pp. 248-259.
35. Q. Wu, P. Juang, M. Martonosi, L.-S. Peh, and D. W. Clark, "Formal control techniques for power-performance management," IEEE Micro, vol.25, no.5, pp. 52-62, Sep./Oct. 2005.
36. P. Van der Wolf, P. Lieverse, M. Goel, D. La Hei, and K. Vissers, "An MPEG-2 decoder case study as a driver for a system level design methodology," in Proc. Int. Symp. Hardw.-Softw. Codesign CODES, 1999, pp. 33-37.
37. D. Zhu, R. Melhem, and B. Childers, "Scheduling with dynamic voltage/ speed adjustment using slack reclamation in multiprocessor real-time systems," IEEE Trans. Parallel Distrib. Syst., vol.14, no.7, pp. 686-700, Jul. 2003.