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Volumn , Issue , 2004, Pages 21-24

Flit admission in on-chip wormhole-switched networks with virtual channels

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COUPLED CIRCUITS; CROSSBAR EQUIPMENT; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PACKET NETWORKS; PERSONAL COMPUTERS; QUEUEING NETWORKS;

EID: 21244466371     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (8)
  • 1
    • 84893760422 scopus 로고    scopus 로고
    • Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures
    • J. Hu and R. Marculescu. Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures. In DATE, 2003.
    • (2003) DATE
    • Hu, J.1    Marculescu, R.2
  • 2
    • 84893753441 scopus 로고    scopus 로고
    • Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
    • E. Rijpkema, K. Goossens, et al. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. In DATE, 2003.
    • (2003) DATE
    • Rijpkema, E.1    Goossens, K.2
  • 4
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In DAC, 2001.
    • (2001) DAC
    • Dally, W.J.1    Towles, B.2
  • 5
    • 3042740415 scopus 로고    scopus 로고
    • Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
    • Mikael Millberg, Erland Nilsson, Rikard Thid, and Axel Jantsch. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In DATE, 2004.
    • (2004) DATE
    • Millberg, M.1    Nilsson, E.2    Thid, R.3    Jantsch, A.4
  • 6
    • 0032001095 scopus 로고    scopus 로고
    • A cost and speed model for k-ary n-cube wormhole routers
    • Feb.
    • A. A. Chien. A cost and speed model for k-ary n-cube wormhole routers. IEEE Transactions on Parallel and Distributed Systems, 9(2):150-162, Feb. 1998.
    • (1998) IEEE Transactions on Parallel and Distributed Systems , vol.9 , Issue.2 , pp. 150-162
    • Chien, A.A.1
  • 7
    • 0035101680 scopus 로고    scopus 로고
    • A delay model for router microarchitectures
    • Jan.-Feb.
    • L. S. Peh and W. J. Dally. A delay model for router microarchitectures. IEEE Micro, pages 26-34, Jan.-Feb. 2001.
    • (2001) IEEE Micro , pp. 26-34
    • Peh, L.S.1    Dally, W.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.