Design of efficient reversible binary subtractors based on a new reversible gate

Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009

Volumn , Issue , 2009, Pages 229-234

  Thapliyal, Himanshu ^a   Ranganathan, Nagarajan ^a  

^a University of South Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GARBAGE OUTPUT; LOW POWER VLSI DESIGN; OPTICAL COMPUTING; QUANTUM COMPUTING; QUANTUM COSTS; QUANTUM DOT CELLULAR AUTOMATA; REVERSIBLE GATES; REVERSIBLE LOGIC; REVERSIBLE LOGIC ELEMENTS; SUBTRACTOR;

CELLULAR AUTOMATA; COMPUTER SCIENCE; LOGIC GATES; OPTICAL DATA PROCESSING; PATTERN RECOGNITION SYSTEMS; QUANTUM COMPUTERS; QUANTUM OPTICS; SEMICONDUCTOR QUANTUM DOTS;

DESIGN;

EID: 70349478846     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2009.49     Document Type: Conference Paper

References (26)

1. R. Landauer, "Irreversibility and Heat Generation in the Computational Process", IBM J. Research and Development, 5, pp. 183-191, 1961.
2. C.H. Bennett, "Logical Reversibility of Computation", IBM J. Research and Development, pp. 525-532, November 1973.
3. A.N. Al-Rabadi, "Reversible Logic Synthesis: From Fundamentals to Quantum Computing", Springer-Verlag, New York, First Edition, 2004
4. V. Vedral, A. Bareno and A. Ekert, "Quantum Networks for Elementary Arithmetic Operations". arXiv:quant-ph/9511018 v1. (nov 1995)
5. H. Thapliyal and N. Ranganathan, "Reversible Logic Based Concurrently Testable Latches for Molecular QCA", To appear IEEE Trans. on Nanotechnology, 2009.
6. D. Maslov, "Reversible Logic Synthesis", Phd. Thesis, University of New Brunswick, Canada, Oct 2003.
7. K. Patel, I. Markov, and J. Hayes, "Optimal Synthesis of Linear Reversible Circuits," Quantum Information and Computation, vol. 8, no. 3-4, pp. 282-294, 2008.
8. A. D. Vos and Y. Van Rentergem, "Power consumption in reversible logic addressed by a ramp voltage", Proc. of the 15th Intl. Workshop Patmos 2005, Lecture Notes of Computer Science, vol. 3728, pp. 207-216, Springer- Verlag, Oct 2005.
9. E. Fredkin, T Toffoli, "Conservative Logic", Int. J. Theor. Phys, vol. 21, no. 3-4, pp. 219-253, 1982
10. T. Toffoli, "Reversible Computing", Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).
11. A. Peres, "Reversible logic and quantum computers," Phys. Rev. A, Gen. Phys., vol. 32, no. 6, pp. 3266- 3276, Dec. 1985.
12. H. Thapliyal and N. Ranganathan, "Testable Reversible Latches for Molecular QCA", Proc. of the 8th Intl. Conf. on Nanotechnology, Arlington, TX, Aug 2008, pp. 699-702.
13. J. Mathew, H. Rahaman, B.R. Jose, D.K. Pradhan, "Design of Reversible Finite Field Arithmetic Circuits with Error Detection", Proc. of the 21st Intl. Conf. on VLSI Design, Hyderabad, India, Jan 2008, pp.453-459.
14. J.W. Bruce, M.A. Thornton, L. Shivakumariah, P.S. Kokate and X.Li, "Efficient Adder Circuits Based on a Conservative Logic Gate", Proc. of the IEEE Computer Society Annual Symposium on VLSI, April 2002, Pittsburgh, PA, USA, pp 83-88.
15. H. M. H. Babu, M. R. Islam, S.M. Ali Chowdhury and A. R.Chowdhury, "Synthesis of Full-Adder Circuit Using Reversible Logic", Proc. of the 17th International Conference on VLSI Design (VLSI Design 2004), January 2004, Mumbai, India,pp-757-760.
16. H. Thapliyal, M.B Srinivas and H.R Arabnia, "Reversible Logic Synthesis of Half, Full and Parallel Subtractors", Proc. of the 2005 Intl. Conf. on Embedded Systems and Applications, June 2005, Las Vegas, pp.165-181.
17. M.P Frank, "Introduction to reversible computing: motivation, progress, and challenges", Proc. of the 2nd Conf. on Computing Frontiers, 2005, pp 385-390.
18. D. Maslov and G. W. Dueck, "Reversible Cascades with Minimal Garbage", IEEE Trans. on CAD, vol. 23(11), pp. 1497-1509, Nov. 2004
19. Digital Signal Processing (DSP) Blocks in Stratix Devices, available online at www.altera.com
20. W.N. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, "Optimal Synthesis of Multiple Output Boolean Functions Using a Set of Quantum Gates by Symbolic Reachability Analysis", IEEE Trans. Computer-Aided Design, Vol. 25, No. 9,pp.1652-1663, Sep 2006.
21. C. Chavet, C. Andriamisaina, P. Coussy, E. Casseau, E. Juin, P. Urard, E. Martin, "A design flow dedicated to multi-mode architectures for DSP applications", Proc.of the IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD07), San Jose, CA, Nov. 2007,pp.604-611
22. H. Thapliyal and N. Ranganathan, "Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits", Proc. of the 22nd Intl. Conf. on VLSI Design, New Delhi, India, Jan 2009, pp. 511-516
23. M.K. Thomsen and R. Glück, "Optimized reversible binary-coded decimal adders", Vol.54, no.7, pp.697- 706, Jul 2008.
24. J. A. Smolin, D. P. DiVincenzo, "Five Two-Bit Quantum Gates are Sufficient to Implement the Quantum Fredkin Gate," Physical Review A, 53, 1996, pp.2855-2856.
25. P. Gupta, A. Agarwal, and N. K. Jha, "An Algorithm for Synthesis of Reversible Logic Ciruits", IEEE Trans. Computer-Aided Design, vol. 25, no. 11, pp. 2317-2330, Nov. 2006
26. X. Ma, J. Huang, C. Metra, F.Lombardi, "Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA", Springer Journal of Electronic Testing, Vol. 24, No. 1-3, pp.297-311, Jan 2008.