Synthesis of full-adder circuit using reversible logic

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 757-760

  Babu, Hafiz Md Hasan ^a   Islam, Md Rafiqul ^a   Chowdhury, Syed Mostahed Ali ^a   Chowdhury, Ahsan Raja ^a  

^a UNIVERSITY OF DHAKA   (Bangladesh)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INFORMATION ANALYSIS; MAPPING; NETWORKS (CIRCUITS); THEOREM PROVING; VECTORS;

GARBAGE OUTPUTS; REVERSIBLE GATES;

LOGIC GATES;

EID: 2342614733     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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2. T. Toffoli, "Reversible Computing", in Automata, Languages and Programming, Springer Verlag, 1980, pp. 632-644.
3. A Khlopotine, M. Perkowski and P. Kerntopf, "Reversible Logic Synthesis by Gate Composition", Proceedings of IWLS 2002, pp. 261-266.
4. Md. M. H. Azad Khan, "Design of Full-adder with Reversible Gates", International Conference on Computer and Information Technology, Dhaka, pp 515-519, 2002.
5. P.D. Picton, "Fredkin Gates as the Basic for Comparison of Different Logic Designs", Synthesis and Optimization of Logic Systems, IEE, London, 1994.
6. J. A. Smolin, and D. P. Di Vincenzo, "Five Two-bit Quantum Gates are Sufficient to Implement the Quantum Fredkin Gate", Physical Review A, 53, pp. 2855-2856.
7. M. Perkowski, et al, "Regularity and Symmetry as a Base for Efficient Realization of Reversible Circuits", proc. Intl. Workshop on Logic Synthesis, pp. 90-95, June 2001.
8. R. Keyes and R. Landauer," Minimal energy dissipation in logic"; I.B.M journal of Research and Development, 14 (1970), pp. 153-157.
9. R. Landauer, "Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research and Development, 5, pp. 183-191, 1961.
10. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury," Reversible Logic Synthesis for Minimization of Full-Adder Circuit", IEEE conference on Digital System Design 03(Euro-Micro DSD'03), pp.50-54, September 2-6, 2003.