A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks

Journal of Semiconductors

Volumn 30, Issue 8, 2009, Pages

  He, Jin ^a   Ma, Chenyue ^a   Zhang, Lining ^a   Zhang, Jian ^a   Zhang, Xing ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

Compact modeling; High k gate stack; Interface trap and charges; Nanoscale MOSFETs; Threshold voltage dynamic behavior; Trapping and detrapping

Indexed keywords

COMPACT MODELING; DE-TRAPPING; HIGH-K GATE STACKS; INTERFACE TRAP AND CHARGES; NANOSCALE MOSFETS;

GENE EXPRESSION; LOGIC GATES; MOSFET DEVICES; NANOSTRUCTURED MATERIALS;

THRESHOLD VOLTAGE;

EID: 70349181432     PISSN: 16744926     EISSN: None     Source Type: Journal    
DOI: 10.1088/1674-4926/30/8/084003     Document Type: Article

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