Modeling of charge trapping induced threshold-voltage instability in high-κ gate dielectric FETs

IEEE Electron Device Letters

Volumn 27, Issue 6, 2006, Pages 489-491

  Liu, Yang ^a   Shanware, Ajit ^b   Colombo, Luigi ^b   Dutton, Robert ^a  

^a Stanford University   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Charge trapping; Field effect transistors (FETs); Hafnium dioxide (HfO2); High dielectric; Tunneling

Indexed keywords

COMPUTER SIMULATION; ELECTRON ENERGY LEVELS; ELECTRON TRAPS; ELECTRON TUNNELING; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; MATHEMATICAL MODELS; THRESHOLD VOLTAGE;

CHARGE TRAPPING; DEVICE -LEVEL SIMULATIONS; HAFNIUM DIOXIDE; TRAP-ENERGY-LEVEL SHIFT;

FIELD EFFECT SEMICONDUCTOR DEVICES;

EID: 33744742930     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.874760     Document Type: Article

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