Low-power high-level synthesis using latches

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 462-465

  Yang, Wooseung ^a   Park, In Cheol ^a   Kyung, Chong Min ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Capacitance; Circuits; Clocks; Digital signal processing; Energy consumption; Energy management; Flip flops; Frequency; High level synthesis; Latches

Indexed keywords

CAPACITANCE; CLOCKS; COMPUTER AIDED DESIGN; DIGITAL SIGNAL PROCESSING; ENERGY MANAGEMENT; ENERGY UTILIZATION; FLIP FLOP CIRCUITS; NETWORKS (CIRCUITS); POWER MANAGEMENT; SIGNAL PROCESSING; SYNTHESIS (CHEMICAL);

CLOCK GATING; CLOCKING SCHEMES; CONVENTIONAL POWER; FREQUENCY; LOW POWER; SHORT TERM; STORAGE ELEMENTS; TWO PHASE;

HIGH LEVEL SYNTHESIS;

EID: 69949143977     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913351     Document Type: Conference Paper

References (8)

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