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Volumn , Issue , 2008, Pages 27-30

ILP-based scheme for timing variation-aware scheduling and resource binding

Author keywords

[No Author keywords available]

Indexed keywords

CASE-BASED APPROACH; CIRCUIT DESIGNS; CIRCUIT TIMING; COMPUTATION TIME; DELAY ANALYSIS; DESIGN SPACE EXPLORATION; HIGH LEVEL SYNTHESIS; INTEGER LINEAR PROGRAMMING; LATENCY REDUCTION; PERFORMANCE ESTIMATION; PROCESS VARIATION; RESOURCE BINDING; TIMING ANALYSIS; TIMING VARIATIONS; TIMING YIELD;

EID: 67650269446     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2008.4641473     Document Type: Conference Paper
Times cited : (8)

References (10)
  • 1
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    • 0348040110 scopus 로고    scopus 로고
    • Block-based static timing analysis with uncertainty
    • A. Devgan and C. Kashyap. Block-based static timing analysis with uncertainty. In ICCAD, pages 607-614, 2003.
    • (2003) ICCAD , pp. 607-614
    • Devgan, A.1    Kashyap, C.2
  • 3
    • 0028135729 scopus 로고
    • ILP-based scheduling with time and resource constraints in high level synthesis
    • S. Chaudhuri and R. A. Walker. ILP-based scheduling with time and resource constraints in high level synthesis. In VLSI Design, pages 17-20, 1994.
    • (1994) VLSI Design , pp. 17-20
    • Chaudhuri, S.1    Walker, R.A.2
  • 5
    • 28444484435 scopus 로고    scopus 로고
    • An ILP formulation for reliability-oriented high-level synthesis
    • S. Tosun, O. Ozturk, and et al. An ILP formulation for reliability-oriented high-level synthesis. In ISQED, pages 364-369, 2005.
    • (2005) ISQED , pp. 364-369
    • Tosun, S.1    Ozturk, O.2    and et, al.3
  • 6
    • 33846118079 scopus 로고    scopus 로고
    • Designing reliable systems from unreliable components: The challenges of transistor variability and degradation
    • S. Borkar. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. Micro, IEEE, 25(6):10-16, 2005.
    • (2005) Micro, IEEE , vol.25 , Issue.6 , pp. 10-16
    • Borkar, S.1
  • 7
    • 46149112172 scopus 로고    scopus 로고
    • Guaranteeing performance yield in high-level synthesis
    • W. L. Hung, X. Wu, and Y. Xie. Guaranteeing performance yield in high-level synthesis. In ICCAD, pages 303-309, 2006.
    • (2006) ICCAD , pp. 303-309
    • Hung, W.L.1    Wu, X.2    Xie, Y.3
  • 8
    • 50249164346 scopus 로고    scopus 로고
    • Timing variation-aware high-level synthesis
    • J. Jung and T. Kim. Timing variation-aware high-level synthesis. In ICCAD, 2007.
    • (2007) ICCAD
    • Jung, J.1    Kim, T.2
  • 9
    • 0025554245 scopus 로고
    • checktc and mintc: Timing verification and optimal clocking of synchronous digital circuits
    • K. A. Sakallah, T. N. Mudge, and O. A. Olukotun. checktc and mintc: Timing verification and optimal clocking of synchronous digital circuits. In ICCAD, pages 552-555, 1990.
    • (1990) ICCAD , pp. 552-555
    • Sakallah, K.A.1    Mudge, T.N.2    Olukotun, O.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.