Tolerating process variations in high-level synthesis using transparent latches

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 73-78

  Chen, Yibo ^a   Xie, Yuan ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIOR SYNTHESIS; DELAY VARIATIONS; FUNCTION UNITS; HIGH-LEVEL SYNTHESIS; OPTIMIZATION FRAMEWORKS; PROCESS VARIABILITIES; PROCESS VARIATIONS; TIME SLACKS; TIMING YIELDS;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; TIME MEASUREMENT;

FLIP FLOP CIRCUITS;

EID: 64549087144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796444     Document Type: Conference Paper

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