-
1
-
-
0035821957
-
Wideband low-distortion AS ADC topology
-
Jun
-
J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, "Wideband low-distortion AS ADC topology," Electron. Lett., vol. 37, no. 12, pp. 737-738, Jun. 2001.
-
(2001)
Electron. Lett
, vol.37
, Issue.12
, pp. 737-738
-
-
Silva, J.1
Moon, U.2
Steensgaard, J.3
Temes, G.C.4
-
2
-
-
4644302408
-
High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling AS ADCs for broadband applications
-
Jan
-
A. A. Hamoui and K. W. Martin, "High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling AS ADCs for broadband applications," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 72-85, Jan. 2004.
-
(2004)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.51
, Issue.1
, pp. 72-85
-
-
Hamoui, A.A.1
Martin, K.W.2
-
3
-
-
33751552173
-
Noise-coupled delta-sigma ADCs
-
Nov
-
K. Lee, M. Bonu, and G. C. Temes, "Noise-coupled delta-sigma ADCs," Electron. Lett., vol. 42, no. 24, pp. 1381-1382, Nov. 2006.
-
(2006)
Electron. Lett
, vol.42
, Issue.24
, pp. 1381-1382
-
-
Lee, K.1
Bonu, M.2
Temes, G.C.3
-
4
-
-
47349091323
-
Enhanced split-architecture delta-sigma ADC
-
Dec
-
K. Lee and G. C. Temes, "Enhanced split-architecture delta-sigma ADC," in Proc. IEEE ICECS 2006, Dec. 2006, pp. 427-430.
-
(2006)
Proc. IEEE ICECS 2006
, pp. 427-430
-
-
Lee, K.1
Temes, G.C.2
-
5
-
-
34548839623
-
Noise-coupled multi-cell delta-sigma ADCs
-
May
-
K. Lee, G. C. Temes, and F. Maloberti, "Noise-coupled multi-cell delta-sigma ADCs," in Proc. IEEE ISCAS 2007, May 2007, pp. 249-252.
-
(2007)
Proc. IEEE ISCAS 2007
, pp. 249-252
-
-
Lee, K.1
Temes, G.C.2
Maloberti, F.3
-
6
-
-
57849113661
-
A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR
-
Dec
-
K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi, and G. C. Temes, "A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2601-2612, Dec. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.12
, pp. 2601-2612
-
-
Lee, K.1
Chae, J.2
Aniya, M.3
Hamashita, K.4
Takasuka, K.5
Takeuchi, S.6
Temes, G.C.7
-
7
-
-
57849132278
-
An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and -98 dB THD
-
Sep
-
K. Lee, M. Miller, and G. C. Temes, "An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and -98 dB THD," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2008, pp. 93-96.
-
(2008)
Proc. IEEE Custom Integrated Circuits Conf. (CICC)
, pp. 93-96
-
-
Lee, K.1
Miller, M.2
Temes, G.C.3
-
9
-
-
0033698077
-
An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC
-
Sep
-
E. Fogleman, J. Welz, and I. Galton, "An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2000, pp. 17-20.
-
(2000)
Proc. IEEE Custom Integrated Circuits Conf. (CICC)
, pp. 17-20
-
-
Fogleman, E.1
Welz, J.2
Galton, I.3
-
10
-
-
0035273851
-
Very low-voltage digital-audio AS modulator with 88-dB dynamic range using local switch bootstrapping
-
Mar
-
M. Dessouky and A. Kaiser, "Very low-voltage digital-audio AS modulator with 88-dB dynamic range using local switch bootstrapping," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 349-355, Mar. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.3
, pp. 349-355
-
-
Dessouky, M.1
Kaiser, A.2
-
11
-
-
0033364066
-
A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications
-
Jul
-
I. Mehr and D. Dalton, "A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications," IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 912-920, Jul. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.7
, pp. 912-920
-
-
Mehr, I.1
Dalton, D.2
-
12
-
-
0033872609
-
A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC
-
Mar
-
I. Mehr and L. Singer, "A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318-325, Mar. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.3
, pp. 318-325
-
-
Mehr, I.1
Singer, L.2
-
13
-
-
0029532111
-
Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging
-
Dec
-
R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging," IEEE Trans. Circuits Syst. II, Analog Digit. Signal. Process., vol. 42, pp. 753-762, Dec. 1995.
-
(1995)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal. Process
, vol.42
, pp. 753-762
-
-
Baird, R.T.1
Fiez, T.S.2
-
14
-
-
34548839092
-
A 0.13 μm CMOS EDGE/ UMTS/WLAN tri-mode ΔΣ ADC with -92 dB THD
-
Feb
-
T. Christen, T. Burger, and Q. Huang, "A 0.13 μm CMOS EDGE/ UMTS/WLAN tri-mode ΔΣ ADC with -92 dB THD," in Proc. IEEE ISSCCDig. Tech. Papers, Feb. 2007, pp. 240-241.
-
(2007)
Proc. IEEE ISSCCDig. Tech. Papers
, pp. 240-241
-
-
Christen, T.1
Burger, T.2
Huang, Q.3
-
15
-
-
33750547476
-
A 14 mW multi-bit ΔΣ modulator with 82 dB SNR and 86 dB DR for ADSL2+
-
Feb
-
S. Kwon and F. Maloberti, "A 14 mW multi-bit ΔΣ modulator with 82 dB SNR and 86 dB DR for ADSL2+," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 161-162.
-
(2006)
Proc. IEEE ISSCC Dig. Tech. Papers
, pp. 161-162
-
-
Kwon, S.1
Maloberti, F.2
-
16
-
-
39749095576
-
A 5.4 mW 2-channel time-interleaved multi-bit ΔΣ modulator with 80 dB SNR and 85 dB DR for ADSL
-
Feb
-
K.-S. Lee, S. Kwon, and F. Maloberti, "A 5.4 mW 2-channel time-interleaved multi-bit ΔΣ modulator with 80 dB SNR and 85 dB DR for ADSL," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 171-172.
-
(2006)
Proc. IEEE ISSCC Dig. Tech. Papers
, pp. 171-172
-
-
Lee, K.-S.1
Kwon, S.2
Maloberti, F.3
-
17
-
-
39049124138
-
An 80/100 MS/s 76.3/70.1 dB SNDR ΔΣ ADC for digital TV receivers
-
Feb
-
Y. Fujimoto, Y. Kanazawa, P. Lo Re, and M. Miyamoto, "An 80/100 MS/s 76.3/70.1 dB SNDR ΔΣ ADC for digital TV receivers," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 76-77.
-
(2006)
Proc. IEEE ISSCC Dig. Tech. Papers
, pp. 76-77
-
-
Fujimoto, Y.1
Kanazawa, Y.2
Lo Re, P.3
Miyamoto, M.4
-
18
-
-
39049096243
-
A 100-MS/s 4-MHz bandwidth 77.3-dB SNDR ΔΣ ADC with a triple sampling technique
-
Sep
-
Y. Kanazawa, Y. Fujimoto, P. Lo Re, and M. Miyamoto, "A 100-MS/s 4-MHz bandwidth 77.3-dB SNDR ΔΣ ADC with a triple sampling technique," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2006, pp. 53-56.
-
(2006)
Proc. IEEE Custom Integrated Circuits Conf. (CICC)
, pp. 53-56
-
-
Kanazawa, Y.1
Fujimoto, Y.2
Lo Re, P.3
Miyamoto, M.4
|