Enhanced split-architecture delta-sigma ADC

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn , Issue , 2006, Pages 427-430

  Lee, Kyehyung ^a   Temes, Gabor C ^a  

^a Oregon State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERRORS; MULTICARRIER MODULATION;

CROSS COUPLINGS; DELTA-SIGMA ADC; INTERNATIONAL CONFERENCES; MISMATCH ERRORS; MULTI-STAGE NOISE SHAPING; NOISE SHAPING; QUANTIZATION ERRORS;

DELTA SIGMA MODULATION;

EID: 47349091323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2006.379816     Document Type: Conference Paper

References (4)

1. J. Li, G. Ahn, D. Chang, and U. Moon: 'A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR', IEEE J. of Solid-State Circuits, vol. 40, no. 4, pp. 960-969, Apr. 2005
2. J. McNeill, M. Coin, and B. Larivee: "Split-ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2437-2445, Dec. 2005
3. Z. Zhang, J. Steensgaard, and G. C. Temes: 'Dual-path delta-sigma modulators', MWSCAS'05, Cincinnati, OH., Aug. 2005
4. J. Silva, U. Moon, J. Steensgaard, and G. C. Temes: 'Wideband low-distortion delta-sigma ADC topology', Electron. Lett., vol. 37, no. 12, pp. 737-738, Jun. 2001