A 100-MS/s 4-MHz bandwidth 77.3-dB SNDR ΔΣ ADC with a triple sampling technique

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 53-56

  Kanazawa, Yusuke ^a   Fujimoto, Yoshihisa ^a   Lo Ré, Pascal ^a   Miyamoto, Masayuki ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITORS; CMOS INTEGRATED CIRCUITS; DIGITAL TELEVISION; MICROPROCESSOR CHIPS; SAMPLING; SIGNAL RECEIVERS;

CLOCK FREQUENCIES; SWLTCHED CAPACITORS;

ANALOG TO DIGITAL CONVERSION;

EID: 39049096243     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320962     Document Type: Conference Paper

References (5)

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2. Y. Fujimoto, Y. Kanazawa, P. Lo Re and M. Miyamoto "An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers," 2006 ISSCC Digest of Technical Papers, pp. 76-77, February 2006.
3. A.A. Hamoui and K. Martin "High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications," IEEE Transactions on Circuits and Systems - I, vol. 51, pp. 72-85, January 2004.
4. P. Balmelli, Q. Huang, "A 14-b 25-MS/s 200mW ΣΔ Modulator in 0.18-μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, pp. 2161-1269, December 2004.
5. E. Siragusa, I. Galton, "A Digitally Enhanced 1.8V 15b 40MS/s CMOS Pipelined ADC," IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2126-2138, December 2004.