An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for digital TV receivers

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Fujimoto, Yoshihisa ^a   Kanazawa, Yusuke ^a   Lore, Pascal ^a   Miyamoto, Masayuki ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; FREQUENCY BANDS; MICROPROCESSOR CHIPS; MODULATORS;

CLOCK FREQUENCY; DIGITAL TV RECEIVERS;

TELEVISION RECEIVERS;

EID: 39049124138     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. Silva, et al., "Wideband Low-Distortion ΔΣ ADC Topology," Electronics Letters, pp. 737-738, June, 2001.
2. A.A. Hamoui, and K.W. Martin, "High-Order Multibit Modulators and Pseudo Data-Weighted-Averaging in Low-Oversampling ΔΣ ADCs for Broad-Band Applications," IEEE Trans. Circuits Syst. I, pp. 72-85, Jan., 2004.
3. E. Siragusa and I. Galton, "A Digitally Enhanced 1.8-V 15-bit 40-Msample/s CMOS Pipelined ADC," IEEE J. Solid-State Circuits, vol. 39, no.12, pp. 2126-2138, Dec., 2004.
4. L. Yao, et al., "1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS" IEEE J. Solid-State Circuits, vol. 39, no.11, pp. 1809-1818, Nov., 2004.