A 5.4mW 2-channel time-interleaved multi-bit ΔΣ modulator with 80dB SNR and 85dB DR for ADSL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Lee, Kye Shin ^a   Kwon, Sunwoo ^a   Maloberti, Franco ^b  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

2-CHANNEL TIME-INTERLEAVING; CHANNEL MISMATCH;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; SIGNAL TO NOISE RATIO;

DELTA SIGMA MODULATION;

EID: 39749095576     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)