Characteristics of an electroless plated-gate transistor

Applied Physics Letters

Volumn 95, Issue 5, 2009, Pages

  Chen, Li Yang ^a   Chen, Huey Ing ^a   Huang, Chien Chang ^a   Huang, Yi Wen ^a   Tsai, Tsung Han ^a   Liu, Yi Chun ^a   Chen, Tai You ^a   Cheng, Shiou Ying ^b   Liu, Wen Chau ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b NATIONAL ILAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATED STRESS; DEPOSITION TECHNIQUE; DEVICE PROPERTIES; DRAIN SATURATION CURRENT; ELECTROCHEMICAL DEPOSITION; ELECTROLESS; ELECTRONIC APPLICATION; FORWARD VOLTAGE; FREE METALS; GATE DEVICES; GATE METALS; GATE TRANSISTORS; GATE-LEAKAGE CURRENT; IDEALITY FACTORS; LOW ENERGIES; LOW TEMPERATURES; OPERATING REGIMES; PSEUDOMORPHIC HIGH ELECTRON MOBILITY TRANSISTORS; SCHOTTKY BARRIER HEIGHTS; SURFACE DAMAGES; TEMPERATURE DEPENDENT; TEMPERATURE RANGE; THERMAL STABILITY;

ELECTRIC POTENTIAL; ELECTRON MOBILITY; HIGH ELECTRON MOBILITY TRANSISTORS; REDUCTION; SCHOTTKY BARRIER DIODES; THERMODYNAMIC STABILITY; TRANSISTORS;

DRAIN CURRENT;

EID: 68349144498     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3202404     Document Type: Article

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