Fermi level pinning and schottky barrier height control at metal-semiconductor interfaces of InP and related materials

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 38, Issue 2 B, 1999, Pages 1098-1102

  Hasegawa, Hideki ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

Author keywords

DIGS model; Electroplating; Fermi level pinning; Indium phosphide; MIGS model; Schottky barrier height

Indexed keywords

DEPOSITION; FERMI LEVEL; SCHOTTKY BARRIER DIODES; SELENIUM; SEMICONDUCTING INDIUM PHOSPHIDE; SEMICONDUCTOR DEVICE MODELS; SULFUR; SURFACE TREATMENT;

DISORDER INDUCED GAP STATE MODEL; ELECTROCHEMICAL DEPOSITION; FERMI LEVEL PINNING; INSULATOR INTERLAYERS; LOW TEMPERATURE METAL DEPOSITION; METAL INDUCED GAP STATE MODEL; METAL SEMICONDUCTOR INTERFACES; PLASMA SURFACE TREATMENT; SCHOTTKY BARRIER HEIGHTS; SEMICONDUCTOR INTERLAYERS;

INTERFACES (MATERIALS);

EID: 0032653022     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.38.1098     Document Type: Article

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