A 3.6pJ/access 480MHz, 128Kbit on-chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability

ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Volumn , Issue , 2008, Pages 278-281

  Cosemans, Stefan ^a   Dehaene, Wim ^a   Catthoor, Francky ^b  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); STATIC RANDOM ACCESS STORAGE;

90NM CMOS; BOOST MODES; ENERGY CONSUMPTIONS; LOW POWER MODES; ON CHIPS; SENSE AMPLIFIERS; SINGLE CYCLES; STOCHASTIC VARIATIONS;

TIMING CIRCUITS;

EID: 58049101024     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681846     Document Type: Conference Paper

References (6)

1. B. Zhai, D. Blaauw, D. Sylvester, S. Hanson, "A Sub-200mV 6T SRAM in 0.13μm CMOS," ISSCC Digest of Technical Papers, pp 332-333, Feb. 2007
2. N. Verma, A. Chandrakasan, 'A 256 kb 65 nm 8T Subthreshold SRAM employing Sense-Amplifier Redundancy," IEEE J. Solid-State Circuits, pp. 141-149, January 2008
3. Y. Wang, H. Ahn, U. Bhattacharya, et al., "A 1.1GHz 12μA/Mb-Leakage SRAM design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications," ISSCC Digest of Technical Papers, pp 324-325, Feb. 2007
4. J. Pille, C. Adams, T. Christensen, et al., "Implementation of the CELL Broadband Engine™ in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3 V," ISSCC Digest of Technical Papers, pp 322-323, Feb. 2007
5. S. Cosemans, W. Dehaene, F.Catthoor, "A Low-Power Embedded SRAM for Wireless Applications," IEEE J. Solid-State Circuits, Vol.42, pp. 1607-1617, July 2007
6. K. Takeda, Y. Hagihara, Y. Aimoto, et al., "A Read-Static-Noise- Margin-Free SRAM Cell for Low-VDD and High-Speed Applications," IEEE J. Solid-State Circuits, Vol.41, pp. 1607-1617, January 2006