A dual port dual width 90nm SRAM with guaranteed data retention at minimal standby supply voltage

ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Volumn , Issue , 2008, Pages 290-293

  Geens, Peter ^a   Dehaene, Wim ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIES; PORTS AND HARBORS; STATIC RANDOM ACCESS STORAGE;

90NM CMOS; ACCESS TIMES; DATA RETENTIONS; DELAY OVERHEADS; DUAL PORTS; LEAKAGE CURRENT REDUCTIONS; SECONDARY SUPPLIES; SUPPLY VOLTAGES;

LEAKAGE CURRENTS;

EID: 58049121594     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681849     Document Type: Conference Paper

References (11)

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