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Unbounded transactional memory
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C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded transactional memory. In Proc. 11th International Symposium on High-Performance Computer Architecture, pages 316-327, Feb. 2005.
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Ananian, C.S.1
Asanovic, K.2
Kuszmaul, B.C.3
Leiserson, C.E.4
Lie, S.5
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52649143372
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Using hardware memory protection to build a high-performance, strongly-atomic hybrid transactional memory
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Washington, DC, USA, IEEE Computer Society
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L. Baugh, N. Neelakantam, and C. Zilles. Using hardware memory protection to build a high-performance, strongly-atomic hybrid transactional memory. In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, pages 115-126, Washington, DC, USA, 2008. IEEE Computer Society.
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Baugh, L.1
Neelakantam, N.2
Zilles, C.3
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3
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65549167440
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Rock: A high-performance SPARC CMT processor
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To appear
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S. Chaudhry, R. Cypher, M. Ekman, M. Karlsson, A. Landin, S. Yip, H. Zeffer, and M. Tremblay. Rock: A high-performance SPARC CMT processor. IEEE Micro, 2009. To appear.
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(2009)
IEEE Micro
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Chaudhry, S.1
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Karlsson, M.4
Landin, A.5
Yip, S.6
Zeffer, H.7
Tremblay, M.8
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4
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Hybrid transactional memory
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Oct
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P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In Proc. 12th Symposium on Architectural Support for Programming Languages and Operating Systems, Oct. 2006.
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Proc. 12th Symposium on Architectural Support for Programming Languages and Operating Systems
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Damron, P.1
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Lev, Y.3
Luchangco, V.4
Moir, M.5
Nussbaum, D.6
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5
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67650091542
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Applications of the adaptive transactional memory test platform
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D. Dice, M. Herlihy, D. Lea, Y. Lev, V. Luchangco, W. Mesard, M. Moir, K. Moore, and D. Nussbaum. Applications of the adaptive transactional memory test platform. Transact 2008 workshop. http://research.sun.com/scalable/pubs/ TRANSACT2008-ATMTP-Apps.pdf.
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Transact 2008 workshop
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Lea, D.3
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Mesard, W.6
Moir, M.7
Moore, K.8
Nussbaum, D.9
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6
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67650067385
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Early experience with a commercial hardware transactional memory implementation
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Technical Report TR-2009-180, Sun Microsystems Laboratories
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D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. Technical Report TR-2009-180, Sun Microsystems Laboratories, 2009.
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(2009)
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Software transactional memory for supporting dynamic-sized data structures
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M. Herlihy, V. Luchangco, M. Moir, and W. N. Scherer III. Software transactional memory for supporting dynamic-sized data structures. In Proc. 22th Annual ACM Symposium on Principles of Distributed Computing, pages 92-101, 2003.
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67650077184
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November, Under submission
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Y. Lev, V. Luchangco, V. Marathe, M. Moir, D. Nussbaum, and M. Olszewski. Anatomy of a scalable software transac-tional memory, November 2008. Under submission.
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(2008)
Anatomy of a scalable software transac-tional memory
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Lev, Y.1
Luchangco, V.2
Marathe, V.3
Moir, M.4
Nussbaum, D.5
Olszewski, M.6
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Split hardware transactions: True nesting of transactions using best-effort hardware transactional memory
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New York, NY, USA, ACM
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Y. Lev and J.-W. Maessen. Split hardware transactions: true nesting of transactions using best-effort hardware transactional memory. In PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, pages 197-206, New York, NY, USA, 2008. ACM.
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Lev, Y.1
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Testing implementations of transactional memory
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New York, NY, USA, ACM
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C. Manovit, S. Hangal, H. Chafi, A. McDonald, C. Kozyrakis, and K. Olukotun. Testing implementations of transactional memory. In PACT '06: Proceedings of the 15th international conference on Parallel architectures and compilation techniques, pages 134-143, New York, NY, USA, 2006. ACM.
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The Adaptive Transactional Memory Test Platform: A tool for experimenting with transactional code for Rock
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M. Moir, K. Moore, and D. Nussbaum. The Adaptive Transactional Memory Test Platform: A tool for experimenting with transactional code for Rock. In Workshop on Transactional Computiung (Transact), 2008. http://research.sun.com/scalable/pubs/TRANSACT2008-ATMTP.pdf.
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Workshop on Transactional Computiung (Transact)
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Moir, M.1
Moore, K.2
Nussbaum, D.3
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Hardware atomicity for reliable software speculation
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New York, NY, USA, ACM
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N. Neelakantam, R. Rajwar, S. Srinivas, U. Srinivasan, and C. Zilles. Hardware atomicity for reliable software speculation. In ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture, pages 174-185, New York, NY, USA, 2007. ACM.
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Virtualizing transactional memory
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Washington, DC, USA
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R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In Proc. 32nd Annual International Symposium on Computer Architecture, pages 494-505, Washington, DC, USA, 2005.
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Rajwar, R.1
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Architectural support for software transactional memory
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Washington, DC, USA, IEEE Computer Society
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B. Saha, A.-R. Adl-Tabatabai, and Q. Jacobson. Architectural support for software transactional memory. In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 185-196, Washington, DC, USA, 2006. IEEE Computer Society.
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Saha, B.1
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34547683554
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LogTM-SE: Decoupling hardware transactional memory from caches
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Washington, DC, USA, IEEE Computer Society
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L. Yen, J. Bobba, M. R. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. LogTM-SE: Decoupling hardware transactional memory from caches. In HPCA '07: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pages 261-272, Washington, DC, USA, 2007. IEEE Computer Society.
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Yen, L.1
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Moore, K.E.4
Volos, H.5
Hill, M.D.6
Swift, M.M.7
Wood, D.A.8
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