Testing implementations of transactional memory

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2006, Issue , 2006, Pages 134-143

  Manovit, Chaiyasit ^a   McDonald, Austen ^c   Hangal, Sudheendra ^b   Kozyrakis, Christos ^c   Chafi, Hassan ^c   Olukotun, Kunle ^c  

^a SUN MICROSYSTEMS   (United States)

^b Magic Lamp Software   (India)

^c STANFORD UNIVERSITY   (United States)

Author keywords

Specification; Testing; Transactional memory; Verification

Indexed keywords

COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS; SCALABILITY; SYNCHRONIZATION;

NON-TRANSACTIONAL OPERATIONS; PARALLEL SOFTWARE; SCALABLE MULTIPROCESSORS; TRANSACTIONAL MEMORY;

COMPUTER TESTING;

EID: 34247164210     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1152154.1152177     Document Type: Conference Paper

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