Graph based analysis of 2-D FPGA routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 1, 1996, Pages 33-44

  Wu, Yu Liang ^a   Tsukiyama, Shuji ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; CONFORMAL MAPPING; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRING; GRAPHIC METHODS; LOGIC GATES; MATHEMATICAL MODELS; NUMERICAL ANALYSIS; POLYNOMIALS;

CHANNEL DENSITY; CONNECTION TOPOLOGY; FIELD PROGRAMMABLE GATE ARRAYS; INTERVAL PACKING PROBLEM; MAPPING RATIO; ROUTING ARCHITECTURES;

COMPUTER AIDED LOGIC DESIGN;

EID: 0029735979     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.486270     Document Type: Article

References (25)

1. M. Ahrens et al, "An FPGA family optimized for high densities and reduced routing delay," in Proc. CICC, 1990, pp. 31.5.1-31.5.4.
2. [2[ Altéra Corp., The Maximalist Handbook, 1990.
3. N. B. Bhat and D. D. Hill, "Roulable technology mapping for LUT FPGA's," in Proc. 1CCD, 1992, pp. 95-98.
4. S. Brown, R. Francis, J. Rose, and Z. G. Vranesic, Field Programmable Gale Arrays. Boston, MA: Kluwer, 1992.
5. S. Brown, J. Rose, and Z. G. Vranesic, "A stochastic model to predict the routability of field-programmable gate arrays," IEEE Trans. ComputerAided Design, vol. 12, pp. 1827-1838, Dec. 1993.
6. S. Brown, "Routing architectures and algorithms for field programmable gale arrays." Ph. D. dissertation, Dept. of Elect. Eng.. Univ. of Toronto, Feb. 1992.
7. S. Brown, J. Rose, and Z. G. Vranesic, "A detailed rouler for fieldprogrammable gate arrays," IEEE Trans. Computer-Aided Design, vol. 11, pp. 620-628, May 1992.
8. S. C. Chang, K. T. Chcng, N. Woo, and M. Marek-Sadowska, "Layout driven logic synthesis for FPGA's," in Proc. DAC, 1994, pp. 308-313.
9. F. Gavril, "The intersection graphs of subtrees in trees are exactly the Chordal graphs," J. Comb. Theory, vol. B16, pp. 47-56, 1974.
10. M. C. Golumbic, Algorithmic Graph Theory and Perfect Graphs. New York: Academic 1980.
11. A. Hashimoto and J. Stevens, "Wire routing by optimizing channel assignment with large apertures," in Proc. 8th Design Automat. Workshop, 1980, pp. 155-169.
12. H. Hsieh et al., "Third-generation architecture boosts speed and density of field programmable gate arrays," in Proc. CICC, 1990, pp. 31.2.1 31.2.7.
13. G. G. Lemieux and S. D. Brown, "A detailed routing algorithm for allocating wire segments in FPGA's," presented at the 4th ACM/SIGDA Physical Design Workshop, 1993.
14. C. L. Liu, Introduction to Combinatorial Mathematics. New York: McGraw-Hill, 1968.
15. C. Mead and L. Conway, Introduction to VIS! System. New York: Addison Wesley, 1980.
16. J. Rose "Locus Route: A parallel global router for standard cells," in Proc. 25th Design Automation Con/, June 1988. pp. 189-195.
17. J. Rose, A. El Gamal, and A. Sangiovanni-Vincentelli, "Architecture of field programmable gate arrays." (invited paper), Proc. IEEE, vol. 81, July 1993.
18. J. Rose and S. Brown, "The effect of switch box flexibility on routability of field programmable gate arrays," in Proc. CICC, 1990, pp. 27.5.1-27.5.4.
19. M. Schlag, J. Kong, and P. K. Chan, "Routability-driven technology mapping for look up table-based FPGA's," in Proc. ICCD, 1992, pp. 86-90.
20. S. Singh, J. Rose. D. Lewis, K. Chung, and P. Chow, "Optimization of field-programmable gate array logic block architecture for speed," in Proc. CICC, 1991, pp. 6.1.1-6.1.6.
21. S, William et al, "A user programmable reconfigurable logic array," in Proc. CICC, 1986, pp. 233-235.
22. B. Tseng, J. Rose, and S. Brown, "Improving FPGA routing architecture using architecture and CAD interactions," in Proc. ICCD, 1992, pp. 99-104.
23. [231 A. Vilial, "A constrained channel routing problem," ECE Dept. UCSB, Fall 1992, unpublished manuscript.
24. Y. L. Wu and M. Marek-Sadowska, "Graph based analysis of FPGA routing," in Proc. EURO DAC with EURO VHDL, 1993, pp. 104-109.
25. Y. L. Wu, S. Tsnkiyaina and M. Marek-Sadowska, "On computational complexity of a detailed routing problem in two-dimensional FPGA's," in Proc. 4th Great Lakes Symp. VLSI, Mar. 1994.