Yield modelling and yield enhancement for FPGAS using fault tolerance schemes

Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 409-414

  Campregher, Nicola ^a   Cheung, Peter Y K ^a   Constantinides, George A ^a   Vasilko, Milan ^b  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b BOURNEMOUTH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS;

FAULT TOLERANCE SCHEMES; INTERCONNECT LAYERS; YIELD ENHANCEMENT; YIELD MODELING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33745808576     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515756     Document Type: Conference Paper

References (12)

1. P. Simon, "Yield modeling for deep sub-micron IC design," PhD Thesis, University of Eindhoven, 2001.
2. C. Stapper, "Modeling of integrated circuit defect sensitivities," IBM Journal of Research and Development, vol. 27, pp. 549-557, 1983.
3. N. Campregher, P. Cheung, G. Constantinides, and M. Vasilko, "Analysis of yield loss due to random photolithographic defects in the interconnect structure of fpgas," in Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, 2005.
4. A. V. Ferris-Prabhu, Introduction to semiconductor device yield modeling, ser. Artech House materials science library. Boston: Artech House, 1992.
5. H. Sato, M. Ikota, A. Sugimoto, and H. Masuda, "A new defect distribution metrology with a consistent discrete exponential formula and its applications," IEEE Transactions on Semiconductor Manufacturing, vol. 12, no. 4, pp. 409-418, 1999.
6. I. A. Wagner and I. Koren, "The effect of spot defects on the parametric yield of long interconnection lines," in Defect and fault tolerance in VLSI systems. Lafayette; LA: IEEE Computer Society Press, 1995, pp. 46-54.
7. R. Garg, "Characteristics of coupled microstriplines," IEEE Transactions on Microwave Theory and Techniques, vol. MTT-27, no. 7, pp. 700-5, 1979.
8. A. K. Goel, High speed VLSI interconnections: modeling, analysis, and simulation, ser. Wiley series in microwave and optical engineering. New York: Wiley-Interscience, 1994.
9. F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, T. Hibi, Y. Saeki, H. Muroga, A. Tanaka, and K. Kanzaki, "Introducing redundancy in field programmable gate arrays," in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 7.1.1-7.1.4.
10. F. Hanchek and S. Dutt, "Methodologies for tolerating cell and interconnect faults in FPGAs," IEEE Transactions on Computers C, vol. 47, no. 1, pp. 15-33, 1998.
11. A. Doumar, S. Kaneko, and H. Ito, "Defect and fault tolerance FPGAs by shifting the configuration data," in Defect and fault tolerance in VLSI systems. Albuquerque; NM: IEEE Computer Society, 1999, pp. 377-385.
12. Semiconductor Industry Association, "The international roadmap for semiconductor," 2004.