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Volumn , Issue , 2006, Pages 455-460

Reconfiguration and fine-grained redundancy for fault tolerance in FPGAS

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANCE; FUZZY LOGIC; INTEGER PROGRAMMING; LINEAR PROGRAMMING; LINEARIZATION; RELIABILITY;

EID: 46249102184     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311251     Document Type: Conference Paper
Times cited : (11)

References (14)
  • 6
    • 46249083734 scopus 로고    scopus 로고
    • F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y Kawahara, T. Hibi, Y Saeki, H. Muroga, A. Tanaka, and K. Kanzaki, Introducing redundancy in field programmable gate arrays, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 7.1.1-7.1.4.
    • F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y Kawahara, T. Hibi, Y Saeki, H. Muroga, A. Tanaka, and K. Kanzaki, "Introducing redundancy in field programmable gate arrays," in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 7.1.1-7.1.4.
  • 7
    • 0031649068 scopus 로고    scopus 로고
    • Methodologies for tolerating cell and interconnect faults in FPGAs
    • F. Hanchek and S. Dutt, "Methodologies for tolerating cell and interconnect faults in FPGAs," IEEE Transactions on Computers C, vol. 47, no. 1, pp. 15-33, 1998.
    • (1998) IEEE Transactions on Computers C , vol.47 , Issue.1 , pp. 15-33
    • Hanchek, F.1    Dutt, S.2
  • 9
    • 84952881229 scopus 로고    scopus 로고
    • Roving STARs: An integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems
    • D. Keymeulen, Ed. Long Beach, CA: IEEE Computer Society
    • M. Abramovici, J. M. Emmert, and C. E. Stroud, "Roving STARs: An integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems," in NASA/DoD workshop on evolvable hardware, D. Keymeulen, Ed. Long Beach, CA: IEEE Computer Society, 2001, pp. 73-92.
    • (2001) NASA/DoD workshop on evolvable hardware , pp. 73-92
    • Abramovici, M.1    Emmert, J.M.2    Stroud, C.E.3
  • 11
    • 0033352290 scopus 로고    scopus 로고
    • S. Dutt, V. Shanmugavel, and S. Trimberger, Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays, in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers, 7-11 Nov. 1999, ser. 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051). San Jose, CA, USA: IEEE, 1999, pp. 173-6.
    • S. Dutt, V. Shanmugavel, and S. Trimberger, "Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays," in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers, 7-11 Nov. 1999, ser. 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051). San Jose, CA, USA: IEEE, 1999, pp. 173-6.
  • 13
    • 46249113976 scopus 로고    scopus 로고
    • S. Yang, Logic synthesis and optimization benchmarks, version 3.0, Microelectronics Centre of North Carolina, 1991
    • S. Yang, "Logic synthesis and optimization benchmarks, version 3.0," Microelectronics Centre of North Carolina, 1991.
  • 14
    • 0013158154 scopus 로고    scopus 로고
    • Architecture and cad for speed and area optimization of fpgas,
    • PhD Thesis, University of Toronto
    • V. Betz, "Architecture and cad for speed and area optimization of fpgas," PhD Thesis, University of Toronto, 1998.
    • (1998)
    • Betz, V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.