Channel-stress study on gate-size effects for damascene-gate pMOSFETs with top-cut compressive stress liner and eSiGe

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 126-127

  Mayuzumi, S ^a   Yamakawa, S ^a   Kosemura, D ^b   Takei, M ^b   Wang, J ^a   Ando, T ^a   Tateshita, Y ^a   Tsukamoto, M ^a   Wakabayashi, H ^a   Ohno, T ^a   Ogura, A ^b   Nagashima, N ^a  

^a SONY CORPORATION   (Japan)

^b MEIJI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL ACOUSTICS; COMPRESSIVE STRESS; TECHNOLOGY; TENSILE STRESS;

AND GATES; CHANNEL STRAIN; DAMASCENE GATE; DAMASCENE GATE PROCESS; GA TE LENGTHS; GATE WIDTHS; P-MOSFETS; SIZE EFFECTS; STRESS ENHANCEMENT; UV-RAMAN SPECTROSCOPY; VLSI TECHNOLOGIES;

MOSFET DEVICES;

EID: 51949110479     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588588     Document Type: Conference Paper

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