Analysis of novel stress enhancement effect based on damascene gate process with eSiGe S/D for pFETs

2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

Volumn , Issue , 2007, Pages 109-112

  Yamakawa, S ^a   Wang, J ^a   Tateshita, Y ^a   Nagano, K ^a   Tsukamoto, M ^a   Ohri, H ^a   Nagashima, N ^a   Ansai, H ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPRESSIVE STRESS; SEMICONDUCTOR DEVICES;

CURRENT ENHANCEMENT; DAMASCENE GATE PROCESS; DEVICE FABRICATIONS; EMBEDDED SIGE (ESIGE); NEW CHANNELS; REPULSIVE FORCES; STRESS ENHANCEMENT; STRESS SIMULATIONS;

SI-GE ALLOYS;

EID: 84901362411     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-211-72861-1_26     Document Type: Conference Paper

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