Characterization of low-k SiOCH dielectric for 45 nm technology and link between the dominant leakage path and the breakdown localization

Microelectronic Engineering

Volumn 85, Issue 10, 2008, Pages 2075-2078

  Vilmay, M ^a   Roy, D ^a   Volpi, F ^b   Chaix, J M ^b  

^a STMICROELECTRONICS   (France)

^b UNIV GRENOBLE ALPES   (France)

Author keywords

Electron trapping; Low k SiOCH dielectric; Microelectronic; Poole Frenkel conduction; Process impact

Indexed keywords

CHARACTERIZATION; HEAT CONDUCTION; NANOTECHNOLOGY; TECHNOLOGY;

45 NM TECHNOLOGY; BAND DIAGRAMS; BREAKDOWN MECHANISM; CONDUCTION MECHANISMS; ELECTRICAL CHARACTERIZATIONS; ELECTRON TRAPPING; ELECTRON-INJECTION; HIGH FIELDS; LOW-K SIOCH DIELECTRIC; MICROELECTRONIC; POOLE-FRENKEL; POOLE-FRENKEL CONDUCTION; POROUS LOW-K; PROCESS IMPACT; PROCESS STEPS;

MECHANISMS;

EID: 52149114894     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2008.04.045     Document Type: Article

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